EXPLORATION OF FULL HD MEDIA DECODING ON SDR BASEBAND PROCESSOR

In recent years, many SDR baseband processors have been proposed to meet the high performance and programmability requirement for emerging wireless communications. To be able to support hundreds of Mbps or even Gbps wireless communications, such SDR baseband processors often have massive parallel computation capability. This promising processing capability may also be exploited for other types of signal processing tasks. Our work explores the feasibility of performing challenging media processing on SDR baseband processors. In this paper, we will show exploratory experiments for supporting full HD H.264/AVC media decoding on a recent version of ADRES based SDR baseband processor. Two computational dominant tasks, motion compensation and deblocking filter, have been selected to experiment on the processor. These two blocks account about 80% of the total execution time. Since the processor is designed to be wireless domain specific, algorithm and architecture co-optimizations are crucial to make the goal feasible. Results show that, with limited architecture extension, the ADRES based baseband processor achieves very competitive performance and efficiency even when compared with several architectures that are specifically optimized for the media decoding.