A Low-Cost Carry Look-Ahead Adder for Flying-Adder Frequency Synthesizer

被引:0
|
作者
Chen, Pao-Lung [1 ]
机构
[1] Natl Kaohsiung First Univ Sci & Technol, Kaohsiung, Taiwan
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a compact and cost-effective carry look-ahead adder for fractional accumulator in flying-adder frequency synthesizer. The fractional accumulator design is critical in flying-adder frequency synthesizer. Conventional carry look-ahead adder is replaced with a two-bit carry look-ahead adder and another D flip-flop to serve as basic module to construct the adder. The power consumption is approximately 59% of conventional approach. The proposed method eliminates the large gate area in conventional method that can greatly reduce the hardware cost. Measurements show that the output frequency error is less than 3 ppm.
引用
收藏
页码:365 / 366
页数:2
相关论文
共 50 条
  • [21] A New Carry Look-Ahead Adder Architecture Optimized for Speed and Energy
    Balasubramanian, Padmanabhan
    Maskell, Douglas L.
    ELECTRONICS, 2024, 13 (18)
  • [22] RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder
    Akbari, Omid
    Kamal, Mehdi
    Afzali-Kusha, Ali
    Pedram, Massoud
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65 (08) : 1089 - 1093
  • [23] VARIANTS OF AN IMPROVED M-VALUED CARRY LOOK-AHEAD ADDER
    HU, ZH
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1991, 71 (05) : 799 - 803
  • [24] Adiabatic carry look-ahead adder with efficient power clock generator
    Mahmoodi-Meimand, H
    Afzali-Kusha, A
    Nourani, M
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2001, 148 (05): : 229 - 234
  • [25] Intrinsic Jitter of Flying-Adder Frequency Synthesizers
    Sotiriadis, Paul P.
    2009 IEEE SARNOFF SYMPOSIUM, CONFERENCE PROCEEDINGS, 2009, : 265 - 268
  • [26] DESIGN AND OPTIMIZATION OF REVERSIBLE LOOK AHEAD CARRY ADDER AND CARRY SAVE ADDER
    Bhuvaneswary, N.
    Lakshmi, A.
    3C TECNOLOGIA, 2020, (SI): : 113 - 126
  • [27] VLSI Implementation of Reduced Resource Allocation for Modified Carry Look-Ahead Adder
    Saptalakar, Bairu K.
    Saptalakar, Shrinivas K.
    Navalagund, S. S.
    Latte, Mrityunjaya V.
    2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT), 2014, : 559 - 564
  • [28] High-Speed and Energy-Efficient Carry Look-Ahead Adder
    Balasubramanian, Padmanabhan
    Mastorakis, Nikos E.
    JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS, 2022, 12 (03)
  • [29] A FRACTIONAL PSEUDO RANDOM BINARY SEQUENCE FOR SPUR REDUCTION IN FLYING-ADDER FREQUENCY SYNTHESIZER
    Chen, Pao-Lung
    Cheng, Chi-Hsin
    2014 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE, ELECTRONICS AND ELECTRICAL ENGINEERING (ISEEE), VOLS 1-3, 2014, : 240 - +
  • [30] Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming
    Lisa, Nusrat Jahan
    Babu, Hafiz Md. Hasan
    2015 28TH INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID), 2015, : 238 - 243