A HIGH SPEED LOW POWER LATCHED COMPARATOR FOR SHA-LESS PIPELINED ADC

被引：2

作者：

Zhao, Lei ^{[1
]}

Yang, Yintang ^{[1
]}

Zhu, Zhangming ^{[1
]}

机构：

[1] Xidian Univ, Inst Microelect, Xian 710071, Peoples R China

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2013年 / 22卷 / 03期

关键词：

Latched comparator; high-speed; low dissipation; pipelined ADC;

D O I：

10.1142/S0218126613500047

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A high speed low power latched comparator is presented. The bipolar junction structures are used to enhance latch speed, and the controller is proposed to reduce latch current drain while providing complementary metal oxide semiconductor (CMOS) level latch signals. The measured delay time of the comparator is 132.5 ps and the power consumption is 127 mu W at 100 MHz. The proposed circuit is used in a 14-bit 100-MSPS SHA-Less pipelined ADC, and is designed by ASMC 0.35-mu m 3.3V BiCMOS technology.

引用

页数：9

共 50 条

[11] SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration
Huang, Pingli
Hsien, Szukang
Lu, Victor
Wan, Peiyuan
Lee, Seung-Chul
Liu, Wenbo
Chen, Bo-Wei
Lee, Yung-Pin
Chen, Wen-Tsao
Yang, Tzu-Yi
Ma, Gin-Kou
Chiu, Yun
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (08) : 1893 - 1903
[12] Split ADC digital background calibration for high speed SHA-less pipeline ADCs
Adel, Hussein
Sabut, Marc
Petigny, Roger
Louerat, Marie-Minerve
2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 1143 - 1146
[13] A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background
王晓飞
张鸿
张杰
杜鑫
郝跃
Journal of Semiconductors, 2016, (03) : 85 - 91
[14] A 12-bit 400-MS/s SHA-Less Pipelined ADC
Luo, Hua
Zhao, Nan
Wei, Qi
Yang, Huazhong
PROCEEDINGS OF 2014 IEEE INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY AND IDENTIFICATION (ASID), 2014, : 55 - 59
[15] A 18 mW 12 bit 50 MS/s SHA-less Pipelined ADC
Xu, Weigang
Gao, Yifan
Liu, Xiaodong
Tang, Zhangwen
2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2017, : 776 - 779
[16] A NOVEL DIGITAL BACKGROUND CALIBRATION TECHNIQUE FOR 16 BIT SHA-LESS MULTIBIT PIPELINED ADC
Narula, Swina
Vashishath, Munish
Pandey, Sujata
ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING, 2016, 14 (05) : 571 - 582
[17] A Low Kick Back Noise Latched Comparator for High Speed Folding and Interpolating ADC
Qi, Yu
Zhang, Guohe
Shao, Zhibiao
Wang, Bo
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 272 - 275
[18] A Low Kick Back Noise Latched Comparator for High Speed Folding and Interpolating ADC
Yu, Qi
Shao Zhibiao
Ting, Chen
Guohe, Zhang
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1965 - 1968
[19] A 10-bit 40MS/s low power SHA-less pipelined ADC for System-On-Chip Digital TV Application
Shylu, D. S.
Moni, D. Jackuline
Pearlin, T. Renita
PROCEEDINGS OF THE 3RD INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS) 2016, 2016, : 309 - 313
[20] A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC
Zhu, Zhangming
Wang, Weitie
Guan, Yuheng
Liu, Shubin
Xiao, Yu
Liu, Lianxi
Yang, Yintang
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2013, 22 (07)

← 1 2 3 4 5 →