A HIGH SPEED LOW POWER LATCHED COMPARATOR FOR SHA-LESS PIPELINED ADC

A high speed low power latched comparator is presented. The bipolar junction structures are used to enhance latch speed, and the controller is proposed to reduce latch current drain while providing complementary metal oxide semiconductor (CMOS) level latch signals. The measured delay time of the comparator is 132.5 ps and the power consumption is 127 mu W at 100 MHz. The proposed circuit is used in a 14-bit 100-MSPS SHA-Less pipelined ADC, and is designed by ASMC 0.35-mu m 3.3V BiCMOS technology.