Reconfigurable half-precision floating-point real/complex fused multiply and add unit

被引：0

作者：

Nesam, J. Jean Jenifer ^{[1
]}

Sivanantham, S. ^{[1
]}

机构：

[1] Vellore Inst Technol, Sch Elect Engn, Vellore 632014, Tamil Nadu, India

来源：

INTERNATIONAL JOURNAL OF MATERIALS & PRODUCT TECHNOLOGY | 2020年 / 60卷 / 01期

关键词：

FMA architecture; floating-point arithmetic; half-precision; FFT processor; reconfigurable system;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Multiplication followed by an addition/subtraction is the common operation in many digital signal and image processing applications. This paper presents a reconfigurable floating-point real/complex fused multiply and add (R/C-FMA) unit using small precision (IEEE-754-2008 16-bit half-precision) format. The developed FMA can be reconfigurable from real to complex based on the control bits. This architecture performs real FMA [(a x b) + c], complex FMA {[(a + ib) x (c + id)] + (e + if)} or mixed real and complex FMA {[(a + ib) x (c + id)] + e}. The field programmable gate array (FPGA) implementation of R/C-FMA design, utilises the modern features of inbuilt DSP blocks for mantissa multiplication and addition/subtraction. The efficient DSP usage for fp16 FMA design shows a 60% reduction in LUT area when compared to conventional fp32 FMA.

引用

页码：58 / 72

页数：15

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