A VLSI architecture for soft-output PR4 detection

被引：0
|
作者：
Gross, WJ [1 ]
Gaudet, VC [1 ]
Gulak, PG [1 ]
机构：
[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON M5S 3G4, Canada
来源：
PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 2000年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 0.35 mum 3-level metal CMOS ASIC is developed for forward-backward soft-output detection of Class-IV partial response signaling. The novel, low-complexity architecture uses a difference metric and a computational kernel implemented as a limiter. The chip was verified to operate at 20 MHz (20 Mbps), the highest speed of our IC tester. Simulations predict operation of up to 150 Mbps.
引用
收藏
页码：416 / 419
页数：4
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