4x4 Multiplier Implementation using Gate Diffusion Input

Addition is a basic component for any operation commonly used in many VLSI systems, such as implementation-specific digital signal processing (DSP) and integrated circuit architecture. Another two important criteria for the design of complete adders would be power consumption and rpm. Full adder architecture with low power consumption and fast latency of more transmission is of great concern in the implementation of modern digital systems. To achieve maximum architecture trade-offs, power delay device or energy consumption per process was added. Digital circuit performance can be optimized through proper logic style selection. In this paper, we design an extended multiplier low power consumption adders to minimize complexity and reduce power consumption compared to other designs. This can increase the speed and reduce the dissipation of power. A newer GDI (Gate Diffusion Input) transmission gate was used to implement the adder configuration. This technology allows reducing the power consumption, delay and area of low-power digital circuits thus dealing with low logic design difficulties.