Simulation of the programming efficiency and the energy consumption of Flash memories during endurance degradation

被引:0
|
作者
Postel-Pellerin, J. [1 ]
Chiquet, P. [1 ]
Della Marca, V. [2 ]
机构
[1] Aix Marseille Univ, CNRS, IM2NP, UMR 7334, 60 Rue F Joliot Curie,Batiment NEEL, F-13453 Marseille 13, France
[2] CNRS, ISEN, IM2NP, Maison Technol,UMR 7334, F-83000 Toulon, France
关键词
Flash memory; endurance degradation; TCAD simulation; current consumption; traps;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper the impact of the endurance degradation on the programming window and the energy consumption of Flash floating gate memories is investigated. We use TCAD simulations to confirm, predict and explain the behavior we have observed in previous experimental studies. These simulations have been developed for 90nm technology node Flash floating gate memories, but they are fully compatible with highly scaled devices. The use of interface traps in the simulation enables to reproduce the increase in the drain current consumption and the decrease in the programming efficiency after endurance degradation. Moreover, we highlight the fact that after degradation the hot electrons energy and velocity are lower, decreasing the electrons injection in the floating gate.
引用
收藏
页码:101 / 104
页数:4
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