Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores

被引：12

作者：

Olivieri, Mauro ^{[1
]}

Cheikh, Abdallah ^{[1
]}

Cerutti, Gianmarco ^{[1
]}

Mastrandrea, Antonio ^{[1
]}

Menichelli, Francesco ^{[1
]}

机构：

[1] Sapienza Univ Rome, DIET, Rome, Italy

来源：

2017 FIRST NEW GENERATION OF CAS (NGCAS) | 2017年

关键词：

D O I：

10.1109/NGCAS.2017.61

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

FPGA-synthesizable soft-processor cores are commonly used in many digital system applications with low medium production volume, to control heterogeneous dedicated computational units and I/O units. In such contexts, the inherently multi-tasking nature of the processor operation demands for a cost-effective and energy-efficient multi-threaded execution, either as multi-core architecture or multi-threaded single-core. This work presents an experimental exploration of microarchitecture design solutions for multi-threaded soft processor core implementations on FPGA. We report detailed quantitative results on resource utilization, performance and energy efficiency of the different solutions, varying the pipeline organizations, thread pool size, active thread count and voltage.

引用

页码：45 / 48

页数：4

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