Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation

被引:39
|
作者
Brooks, Lane [1 ]
Lee, Hae-Seung [1 ]
机构
[1] MIT, Dept Elect Engn & Comp Sci, Cambridge, MA 02139 USA
关键词
Adaptive digital background calibration; capacitor mismatch; finite opamp gain; pipelined analog-to-digital converter (ADC); static nonlinearity;
D O I
10.1109/TCSI.2008.925373
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A method of indirect background digital calibration of the dominant static nonlinearities in pipelined analog-to-digital converters (ADC) is presented. The method, called decision boundary gap estimation (DBGE), monitors the output of the ADC to estimate the size of code gaps that result at the decision boundaries of each stage. Code gaps result from such effects as capacitor mismatch, finite opamp gain, finite current source output impedance, comparator offset, and charge injection. DBGE does not require special calibration signals or additional analog hardware and can even reduce the performance requirements of the analog circuitry. The calibration is performed using the input signal and thus requires that the input signal exercise the codes in the vicinity of the decision boundaries of each stage. If it does not exercise these codes, then lack of calibration is less critical because the nonlinearities will not appear in the output signal. DBGE is simple and amenable to hardware and/or software implementations. Simulation results indicate DBGE is highly accurate, robust, and adaptive even in the presence of parameter drift and circuit noise.
引用
收藏
页码:2969 / 2979
页数:11
相关论文
共 50 条
  • [21] Digital background calibration of capacitor-mismatch errors in pipelined ADCs
    Taherzadeh-Sani, Mohammad
    Hamoui, Anas A.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (09) : 966 - 970
  • [22] A statistics-based digital background calibration technique for pipelined ADCs
    Mafi, Hamidreza
    Mohammadi, Reza
    Shamsi, Hossein
    INTEGRATION-THE VLSI JOURNAL, 2015, 51 : 149 - 157
  • [23] A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs
    Ding, Bowen
    Miao, Peng
    Li, Fei
    Gu, Weiqi
    IEICE ELECTRONICS EXPRESS, 2022, 19 (04):
  • [24] Convergence analysis of a background interstage gain calibration technique for pipelined ADCs
    Wang, D
    Keane, JP
    Hurst, PJ
    Levy, BC
    Lewis, SH
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4058 - 4061
  • [25] A robust background calibration technique for switched-capacitor pipelined ADCs
    Fan, JL
    Wu, JT
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1374 - 1377
  • [26] Equalization-Based Digital Background Calibration Technique for Pipelined ADCs
    Zeinali, Behzad
    Moosazadeh, Tohid
    Yavari, Mohammad
    Rodriguez-Vazquez, Angel
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (02) : 322 - 333
  • [27] Perturbation-Based Digital Background Calibration Technique for Pipelined ADCs
    Chung, Yung-Hui
    2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 1316 - 1319
  • [28] A Split-Based Digital Background Calibration Technique in Pipelined ADCs
    Hung, Li-Han
    Lee, Tai-Cheng
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2009, 56 (11) : 855 - 859
  • [29] A Maximum-Likelihood-Estimation-based Digital Background Calibration Technique for Interstage Gain Error in Pipelined ADCs
    Cao, Tianxiang
    Xu, Zhiwei
    Han, Shuai
    Ding, Kaijie
    Zhu, Jiang
    2024 9TH INTERNATIONAL CONFERENCE ON COMPUTER AND COMMUNICATION SYSTEMS, ICCCS 2024, 2024, : 167 - 171
  • [30] Background calibration algorithm for 3-stage pipelined-SAR ADCs
    Dong, Peng
    Zhang, Yang
    Mei, Fengyi
    PROCEEDINGS OF 2019 INTERNATIONAL CONFERENCE ON IMAGE, VIDEO AND SIGNAL PROCESSING (IVSP 2019), 2019, : 81 - 84