FPGA implementation of the high-speed floating-point operation

被引：0

作者：

Ji, XS ^{[1
]}

Wang, SR ^{[1
]}

机构：

[1] Southern Univ, Sch Commun&Control, Wuxi 214063, Jiangsu, Peoples R China

来源：

ICEMI 2005: Conference Proceedings of the Seventh International Conference on Electronic Measurement & Instruments, Vol 3 | 2005年

关键词：

floating-point operation; FPGA; triple data path;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, algorithms of the floating-pointmultiplication and addition are discussed. The modified Booth algorithm is founded to be an ideal algorithm Without considering the sign of the multiplier and the multiplicand, modifying the product can be eliminated and the operation speed of the multiplier is improved greatly. A low-power triple data-path architecture can be used to finish the addition.. where the prediction of the leading-one can be operated in paralleled with the subtraction of mantissa. It greatly reduces the delay of the whole floating-point adder. The floating-point operation is also implemented and synthesized in the Altera field programmable gate array (FPGA).

引用

页码：626 / 629

页数：4

共 50 条

[21] Tackling Gaps in Floating-Point Arithmetic: Unum Arithmetic Implementation on FPGA
Hou, Junjie
Zhu, Yongxin
Shen, Yulan
Li, Mengjun
Wu, Han
Song, Han
2017 19TH IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS (HPCC) / 2017 15TH IEEE INTERNATIONAL CONFERENCE ON SMART CITY (SMARTCITY) / 2017 3RD IEEE INTERNATIONAL CONFERENCE ON DATA SCIENCE AND SYSTEMS (DSS), 2017, : 615 - 616
[22] FPGA Based Implementation of a Double Precision IEEE Floating-Point Adder
Ghosh, Somsubhra
Bhattacharyya, Prarthana
Dutta, Arka
7TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO 2013), 2013, : 271 - 275
[23] A FPGA implementation of an open-source floating-point computation system
Brunelli, Claudio
Garzia, Fabio
Nurmi, Jari
Mucci, Claudio
Campi, Fabio
Rossi, Davide
2005 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, 2005, : 29 - 32
[24] Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA
Jaiswal, Manish Kumar
Chandrachoodan, Nitin
IEEE REGION 10 COLLOQUIUM AND THIRD INTERNATIONAL CONFERENCE ON INDUSTRIAL AND INFORMATION SYSTEMS, VOLS 1 AND 2, 2008, : 334 - 337
[25] FPGA Implementation of CORDIC Algorithms for Sine and Cosine Floating-Point Calculations
Sergiyenko, Anatoliy
Moroz, Leonid
Mychuda, Lesya
Samotyj, Volodymir
PROCEEDINGS OF THE THE 11TH IEEE INTERNATIONAL CONFERENCE ON INTELLIGENT DATA ACQUISITION AND ADVANCED COMPUTING SYSTEMS: TECHNOLOGY AND APPLICATIONS (IDAACS'2021), VOL 1, 2021, : 383 - 386
[26] Parameterisable floating-point operations on FPGA
Lee, B
Burgess, N
THIRTY-SIXTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS - CONFERENCE RECORD, VOLS 1 AND 2, CONFERENCE RECORD, 2002, : 1064 - 1068
[27] Floating-point matrix product on FPGA
Bensaali, Faycal
Amira, Abbes
Sotudeh, Reza
2007 IEEE/ACS INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS, VOLS 1 AND 2, 2007, : 466 - +
[28] Floating-Point FPGA: Architecture and Modeling
Ho, Chun Hok
Yu, Chi Wai
Leong, Philip
Luk, Wayne
Wilton, Steven J. E.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (12) : 1709 - 1718
[29] FPGA implementation of floating-point LMS adaptive filters using high-level synthesis
Ushenina, Inna, V
VESTNIK TOMSKOGO GOSUDARSTVENNOGO UNIVERSITETA-UPRAVLENIE VYCHISLITELNAJA TEHNIKA I INFORMATIKA-TOMSK STATE UNIVERSITY JOURNAL OF CONTROL AND COMPUTER SCIENCE, 2022, (59): : 108 - 116
[30] Efficient floating-point implementation of high-order (N)LMS adaptive filters in FPGA
Tichy, Milan
Schier, Jan
Gregg, David
RECONFIGURABLE COMPUTING: ARCHITECTURES AND APPLICATIONS, 2006, 3985 : 311 - 316

← 1 2 3 4 5 →