A CMOS Low-Power Lock-In Amplifier

A novel analog lock-in amplifier designed in a 0.18 mu m CMOS process with a single supply voltage of 1.8 V is presented in this paper. The proposed architecture recovers the signal of interest from noisy environments with errors below 5% for noise signals of the same amplitude as the signal of interest. The lock-in amplifier is suitable for portable applications thanks to its reduced power consumption and single-supply voltage operation. Post-layout simulation results show a variable DC gain ranging from 20 to 40 dB, input-referred noise of 28.1 mu V-rms, power consumption of 350.9 mu W and area of (205x58) mu m(2).