Experimental realization of a two-dimensional to two-dimensional tunnel transistor

We report on the fabrication of an InP-based two-dimensional to two-dimensional tunnel transistor with two modulation-doped strained In0.75Ga0.25As quantum wells of different thickness. The channels are separated by a 10 nm thick InP barrier. Source and drain contacts are realized by non-alloyed ohmic contacts to the upper strained InGaAs layer without short circuit to the second layer. An (NH4)(2)S passivation technique was used to minimize the interface state density and to enable gate control through a SiO2 gate oxide. Below 120 K the transistor shows distinct tunnel effects. The drain current has a negative differential resistance at high gate voltages with a peak to valley ratio bf up to 3.7, whereas at low gate voltages a sudden increase of the drain current by a factor of 2.8 can be observed at a certain gate voltage.