Fully integrated clock generating PLL using low frequency reference signal

被引：0
|
作者：
Aaltonen, L [1 ]
Saukoski, M [1 ]
Halonen, K [1 ]
机构：
[1] Aalto Univ, Elect Circuit Design Lab, FIN-02150 Espoo, Finland
来源：
BEC 2004: PROCEEDING OF THE 9TH BIENNIAL BALTIC ELECTRONICS CONFERENCE | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a fully integrated PLL for clock generation purposes. The PLL, implementation of which is verified through measurements, has its reference frequency in the order of a few kilohertz. The reference is a low frequency, low phase noise signal achieved for example from it mechanical oscillator. Its frequency is multiplied by PLL in powers of two. Also 1/f- and white noise sources causing phase noise are considered.
引用
收藏
页码：87 / 90
页数：4
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