Scalable hybrid verification of complex microprocessors

被引：0
|
作者：
Mneimneh, M [1 ]
Aloul, F [1 ]
Weaver, C [1 ]
Chatterjee, S [1 ]
Sakallah, K [1 ]
Austin, T [1 ]
机构：
[1] Univ Michigan, Ann Arbor, MI 48109 USA
来源：
38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001 | 2001年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We introduce a new verification methodology for modem microprocessors that uses a simple checker processor to validate the execution of a companion high-performance processor. The checker can be viewed as an at-speed emulator that is formally verified to be compliant to an ISA specification. This verification approach enables the practical deployment of formal methods without impacting overall performance.
引用
收藏
页码：41 / 46
页数：6
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