Pre-silicon MOSFET Mismatch Modeling for Early Circuit Simulations

The continuing scaling down of CMOS technologies contributes to the important of having early circuit simulations even before any real silicon data are available. This paper presents a methodology to extract a pre-silicon MOSFET mismatch model using backward propagation of variance (BPV) technique. All the required steps such as the correlation of process and electrical parameters through BSIM3v3 SPICE model and explanation of mathematical relationships among the parameters are discussed. The experimental data for mismatch analysis are projected from 0.35 um process to 0.25 um and 0.18 um processes using the technology scaling coefficient coupled with the related statistical data analysis. The good agreement between experimental and Monte Carlo SPICE simulation data verifies the proposed extraction methodology.