Interpreting Local Variables in AMS Assertions During Simulation

被引：3

作者：

Ain, Antara ^{[1
]}

Dasgupta, Pallab ^{[2
]}

机构：

[1] Indian Inst Technol Kharagpur, Adv Technol Dev Ctr, Kharagpur 721302, W Bengal, India

[2] Indian Inst Technol Kharagpur, Dept Comp Sci & Engn, Kharagpur 721302, W Bengal, India

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2019年 / 38卷 / 05期

关键词：

Analog and mixed-signal (AMS)-assertions; local variables; simulation; ANALOG;

D O I：

10.1109/TCAD.2018.2824288

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The support for local variables in SystemVerilog assertions significantly enhances its expressive power. Handling local variables in analog and mixed-signal (AMS) extensions of assertion languages is tricky due to the dense time interpretation of AMS assertions, and has not been adequately treated in existing literature. This paper presents an approach for interpreting local variables in AMS assertions during simulation and a tool flow that works with standard mixed-mode simulators.

引用

页码：980 / 984

页数：5

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