High-speed FPGA Implementation of an Improved LMS Algorithm

被引：0
|
作者：
Dong, Xianglei [1 ]
Li, Huiyong [1 ]
Wang, Yu [1 ]
机构：
[1] Univ Elect Sci & Technol China, Sch Elect Engn, Chengdu 610054, Sichuan, Peoples R China
来源：
2013 INTERNATIONAL CONFERENCE ON COMPUTATIONAL PROBLEM-SOLVING (ICCP) | 2013年
关键词：
FPGA; adaptive filtering; PDLMS; parallel processing;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
The FPGA implementation of a new parallel processing method is studied by introducing the parallel processing method into the delayed least mean square (DLMS) algorithm. The parallel delayed least mean square (PDLMS) algorithm has the faster data throughput and higher convergence rate than the DLMS algorithm. In this paper, the hardware implementation of PDLMS is realized by hardware description language, while the simulation structure is presented. The results show that the PDLMS algorithm has certain superiority according to DLMS.
引用
收藏
页码：342 / 345
页数：4
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