Performance comparison of throughput between AVC, HEVC and VVC hardware CABAC decoder

This paper proposes a performance comparison of throughput between context-based adaptive binary arithmetic decoding (CABAC) processes adopted in the three recent video codecs: advanced video coding (AVC), high efficiency video coding (HEVC), and versatile video coding (VVC). Consequently, in order to highlight the performance and the modification in three CABAC versions: the three main stages of CABAC decoding Context Selection and Modeling (CSM), Binary Arithmetic Decoding (BAD) and De-binarization (DBZ) are designed, described in VHDL language and implemented on Field Programmable Gate Array (FPGA) device. Firstly, the most efficient CSM is obtained for CABAC VVC with maximum frequency of 183.8 MHz and low power consumption of 0.346 mW. Secondly, the BAD in RM is modified only in the last video standard VVC. The most efficient design of BAD RM is given in the AVC and HEVC version of CABAC with maximum frequency of 261.75 MHz. Thirdly, the BAD in BM and TM are the same adopted in the three CABAC version, with maximum frequencies of 439.657 MHz and 798.861 MHz, respectively. Thirdly, the de-binarization codes are also the same adopted in the three last CABAC versions. Consequently, high frequency of 789.26 MHz is obtained in DBZ but the resources cost and power consumption are greater than that given in CSM and BAD stages. Finally, high throughput of 178.13 bins/s is given by our proposed design of VVC CABAC decoder.