Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration

For a Phase-Locked Loop (PLL), the variation of its output clock cycle time known as clock jitter is an important performance metric. A complete online clock jitter measurement is often performed in two stages - quantization of the clock cycle times into digital codes, and calibration of the digital codes into absolute jitter information in pico-seconds. The latter stage could be challenging as it requires accurate training clock signals as references. In this article, we propose a dithering-based scheme to resolve this issue with ease. For a cell-based PLL using a 90nm CMOS process, the post-layout transistor-level simulation supports that this is a simple yet effective method.