An FPGA-Implemented Antinoise Fuzzy Recurrent Neural Network for Motion Planning of Redundant Robot Manipulators

被引：6
|
作者：
Zhang, Zhijun [1 ,2 ,3 ,4 ,5 ,6 ]
He, Haotian [1 ]
Deng, Xianzhi [1 ]
机构：
[1] South China Univ Technol, Sch Automation Sci & Engn, Guangzhou, Peoples R China
[2] Guangdong Univ Petrochem Technol, Sch Automation, Maoming 525000, Peoples R China
[3] Guangdong Artificial Intelligenceand Digital Econ, Pazhou Lab, Guangzhou 510335, Peoples R China
[4] Shaanxi Univ Technol, Sch Mech Engn, Shaanxi Prov Key Lab Ind Automa t, Hanzhong, Peoples R China
[5] Hunan Univ Finance & Econ, Sch Informat Technol and Management, Changsha 410205, Peoples R China
[6] East China Jiaotong Univ, Sch Automation Sci & Engn, Nanchang, Peoples R China
来源：
IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS | 2024年 / 35卷 / 09期
关键词：
Manipulators; Robots; Planning; Field programmable gate arrays; Convergence; Recurrent neural networks; Artificial neural networks; Field programmable gate array (FPGA); fuzzy control; recurrent neural network (RNN); robot manipulator; time-varying problem; KINEMATIC CONTROL; DESIGN; FORMULATION; CONTROLLER; HARDWARE; SYSTEMS; MODELS;
D O I：
10.1109/TNNLS.2023.3253801
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
When a robot completes end-effector tasks, internal error noises always exist. To resist internal error noises of robots, a novel fuzzy recurrent neural network (FRNN) is proposed, designed, and implemented on field-programmable gated array (FPGA). The implementation is pipeline-based, which guarantees the order of overall operations. The data processing is based on across-clock domain, which is beneficial for computing units' acceleration. Compared with traditional gradient-based neural networks (NNs) and zeroing neural networks (ZNNs), the proposed FRNN has faster convergence rate and higher correctness. Practical experiments on a 3 degree-of-freedom (DOs) planar robot manipulator show that the proposed fuzzy RNN coprocessor needs 496 lookup table random access memories (LUTRAMs), 205.5 block random access memories (BRAMs), 41 384 lookup tables (LUTs), and 16 743 flip-flops (FFs) of the Xilinx XCZU9EG chip.
引用
收藏
页码：12263 / 12275
页数：13
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