A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler

被引：0
|
作者：
Cho, Seoung-geun [1 ]
Kang, Jin-Ku [1 ]
机构：
[1] Inha Univ, Sch Elect & Comp Engn, Incheon, South Korea
来源：
2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE, ISOCC | 2023年
基金：
新加坡国家研究基金会;
关键词：
PAM-4; Receiver; Baud-rate CDR; Time-domain; Jitter Tolerance; Transition Density;
D O I：
10.1109/ISOCC59558.2023.10396550
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes a pulse amplitude modulation-4 (PAM-4) baud-rate clock and data recovery circuit that improves phase detector (PD) gain by increasing transition density. The proposed idea is that one sampler (shared sampler) serves as a data sampler and an error sampler simultaneously to minimize the number of samplers. It can reduce power consumption while having a high phase detector gain. In addition, the accuracy of the early/late signal is improved through the pattern dependent phase detector. Simulation result shows power consumption of the proposed receiver is 0.79[pJ/bit] at -17.8dB channel loss. This work is designed using 65nm process.
引用
收藏
页码：115 / 116
页数：2
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