Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors

被引:2
|
作者
Trommer, J. [1 ]
Bhattacharjee, N. [1 ]
Mikolajick, T. [1 ]
Huhn, S. [2 ]
Merten, M. [2 ]
Djeridane, M. E. [2 ]
Hassan, M. [2 ]
Drechsler, R. [2 ]
Rai, S. [3 ]
Kavand, N. [3 ]
Darjani, A. [3 ]
Kumar, A. [3 ]
Sessi, V. [4 ]
Drescher, M. [4 ]
Kolodinski, S. [4 ]
Wiatr, M. [4 ]
机构
[1] NaMLab gGmbH, Nothnitzer Str 64a, D-01187 Dresden, Germany
[2] Univ Bremen, Arbeitsgrp Rechnerarchitektur, Bibliothekstr 5, D-28359 Bremen, Germany
[3] Tech Univ Dresden, Chair Processor Design, Helmholtzstr 10, D-01062 Dresden, Germany
[4] GlobalFoundries Fab 1, Wilschdorfer Landstr 101, D-01109 Dresden, Germany
关键词
Emerging devices; reconfigurable circuits; EDA; modelling; CMOS co-integration; hardware security; HARDWARE SECURITY; FUNCTIONALITY; MEMORY;
D O I
10.23919/DATE56975.2023.10136918
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Reconfigurable transistors are a new emerging type of device, which offer the promise to improve the resistance of electronic components against know-how theft. In order to enable a product development of such an emerging device, a cross-layer design enablement strategy is needed, as emerging technologies are not necessarily compatible withstandard tools used in the industry. In 'CirroStrato', we aim on the development of such a complete flow enabling CMOS co-integration of reconfigurable transistors, ranging from process adjustments, device modeling, library characterization, physical and logical synthesis up towards sophisticated hardware security tests. In this multi-partner-project (MPP) paper, our aim is to elucidate the overall design enablement flow, as well as current research challenges on the individual stages.
引用
收藏
页数:6
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