High-Order Masking of Lattice Signatures in Quasilinear Time

被引:4
|
作者
del Pino, Rafael [1 ]
Prest, Thomas [1 ]
Rossi, Melissa [2 ]
Saarinen, Markku-Juhani O. [3 ]
机构
[1] PQShield SAS, Paris, France
[2] ANSSI, Paris, France
[3] PQShield LTD, Oxford, England
来源
2023 IEEE SYMPOSIUM ON SECURITY AND PRIVACY, SP | 2023年
关键词
Post-Quantum Cryptography; Side-Channel Security; Masking Countermeasures; Raccoon signature; CONCRETE;
D O I
10.1109/SP46215.2023.10179342
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In recent years, lattice-based signature schemes have emerged as the most prominent post-quantum solutions, as illustrated by NIST's selection of Falcon and Dilithium for standardization. Both schemes enjoy good performance characteristics. However, their efficiency dwindles in the presence of side-channel protections, particularly masking - perhaps the strongest generic side-channel countermeasure. Masking at order d-1 requires randomizing all sensitive intermediate variables into d shares. With existing schemes, signature generation complexity grows quadratically with the number of shares, making high-order masking prohibitively slow. In this paper, we turn the problem upside-down: We design a lattice-based signature scheme specifically for sidechannel resistance and optimize the masked efficiency as a function of the number of shares. Our design avoids costly operations such as conversions between arithmetic and boolean encodings (A2B/B2A), masked rejection sampling, and does not require a masked SHAKE implementation or other symmetric primitives. The resulting scheme is called Raccoon and belongs to the family of Fiat-Shamir with aborts lattice-based signatures. Raccoon is the first lattice-based signature whose key generation and signing running time has only an O(d log(d)) overhead, with d being the number of shares. Our Reference C implementation confirms that Raccoon's performance is comparable to other state-of-the-art signature schemes, except that increasing the number of shares has a near-linear effect on its latency. We also present an FPGA implementation and perform a physical leakage assessment to verify its basic security properties.
引用
收藏
页码:1168 / 1185
页数:18
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