NPRC-I/O: An NoC-Based Real-Time I/O System With Reduced Contention and Enhanced Predictability

被引:0
|
作者
Jiang, Zhe [1 ,2 ]
Dai, Xiaotian [3 ]
Wei, Ran [2 ]
Gray, Ian [3 ]
Gu, Zonghua [4 ]
Zhao, Qingling [5 ]
Zhao, Shuai [6 ]
机构
[1] Southeast Univ, Nanjing 211189, Peoples R China
[2] Univ Cambridge, Cambridge CB2 1TN, England
[3] Univ York, York YO10 5GH, England
[4] Umea Univ, S-90187 Umea, Sweden
[5] Nanjing Univ Sci & Technol, Nanjing 210094, Peoples R China
[6] Sun Yat sen Univ, Guangzhou 510275, Peoples R China
关键词
Architecture; microarchitecture; Network-on-Chip (NoC); real-time;
D O I
10.1109/TCAD.2023.3288511
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
All systems rely on inputs and outputs (I/Os) to perceive and interact with their surroundings. In safety-critical systems, it is important to guarantee both the performance and time-predictability of I/O operations. However, with the continued growth of architectural complexity in modern safety critical systems, satisfying such real-time requirements has become increasingly challenging due to complex I/O transaction paths and extensive hardware contention. In this article, we present a new Network-on-Chip (NoC)-based Predictable I/O system framework (NPRC-I/O) which reduces this contention and ensures the performance and time-predictability of I/O operations. Specifically, NPRC-I/O contains a programmable I/O command controller (NPRC-CC) and a run-time reconfigurable NoC ((RNoC)-No-2), which provides the capability to adjust I/O transaction paths at run time. Using this flexibility, we construct an end-to-end transmission latency analysis and an optimization engine that produces configurations for NPRCI/O and the I/O traffic in a given system. The constructed analysis and optimization engine guarantee the timing of all hard realtime traffic while reducing the deadline misses of soft real-time traffic and overall transmission latency.
引用
收藏
页码:4629 / 4642
页数:14
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