Dual-Gate Silicon Nanowire FET with a Corner Spacer for High-Performance and High-Frequency Applications

Parasitic capacitance in extremely scaled devices is a major issue in device/circuit design. Its contribution to the total device capacitance is very large, especially in nanowire field-effect transistors (FET), which results in poor radio frequency (RF) performance, leading to low values of the maximum oscillation frequency f(MAX)and cut-off frequency f(T). In this work, we have used a corner spacer in a novel dual-gate silicon nanowire FET. A coaxial inner gate has been used in addition to the outer gate, and the channel is sandwiched between them, resulting in a higher drive current, lower threshold voltage, better short-channel performance, and an overall improved performance. This gate/channel engineered nanowire FET with a coaxial inner gate has not been previously reported. We have shown that the parasitic capacitance of nanowire with a corner spacer design is 28.6% less than nanowire FET with a full nitride spacer. Moreover, the f(MAX) and f(T) of the corner spacer design are 30.2% and 15.7% higher than those of the nanowire FET with full nitride spacer design. In this work, we have shown that a well-designed nanowire with a corner spacer can enhance the device performance for sub-10-nm technology nodes.