Universal Compact Model of Flicker Noise in Ferroelectric Logic and Memory Transistors

被引：2

作者：

Kumar, Abhishek ^{[1
]}

Ehteshamuddin, M. ^{[1
]}

Gaidhane, Amol D. ^{[2
]}

Bulusu, Anand ^{[1
]}

Mehrotra, Shruti ^{[3
]}

Dasgupta, Avirup ^{[1
]}

机构：

[1] Indian Inst Technol Roorkee, Dept Elect & Commun Engn, Roorkee 247667, India

[2] Arizona State Univ, Dept EECS, Tempe, AZ 85281 USA

[3] GlobalFoundries, Bengaluru 560045, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2024年 / 71卷 / 01期

关键词：

Compact model; ferroelectric (FE) field effect transistors (FETs); flicker noise; negative capacitance FET (NCFET);

D O I：

10.1109/TED.2023.3287825

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this article, we present a physics-based compact model of flicker noise (low-frequency noise) in ferroelectric (FE) field-effect transistors (FETs). This model predicts the noise due to charge trapping/de-trapping in the FE/dielectric interface accounting for both carrier number fluctuations and correlated mobility fluctuations in the channel. This model can work with any FE framework and has been tested with Landau based as well as nucleation-limited-switching (NLS)-based cores. The effect of FE thickness scaling is also captured. The model is validated for both logic and memory devices with TCAD as well as experimental measurements.

引用

页码：18 / 22

页数：5

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