FPGA implementation of hardware accelerated RTOS based on real-time event handling

被引：1

作者：

Zagan, Ionel ^{[1
,2
]}

Gaitan, Vasile Gheorghita ^{[1
,2
]}

机构：

[1] Stefan cel Mare Univ Suceava, Suceava 720229, Romania

[2] Stefan cel Mare Univ, Integrated Ctr Res Dev & Innovat Adv Mat Nanotechn, Suceava, Romania

来源：

JOURNAL OF SUPERCOMPUTING | 2023年 / 79卷 / 11期

关键词：

nMPRA architecture; Hardware RTOS; Fast context switch; Resource multiplication; PRIORITY QUEUE ARCHITECTURES; PROCESSOR;

D O I：

10.1007/s11227-023-05151-0

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Actual trends in the real-time system field consists of migration towards complex central processing unit (CPU) architectures with enhanced execution predictability and rapid CPU contexts switch, thus obtaining high-performant control systems. The main objective of this paper is to present the results obtained following the implementation of real-time operating systems (RTOS) functions in hardware. Based on the CPU resource multiplication concept, actual researches has been focused on synthesizing in field-programmable gate array (FPGA) and implementing innovative solutions to improve RTOS performance. The results are materialized by validating an efficient hardware scheduler micro-architecture, from which a remarkable efficiency and a plus of performance and predictability are obtained. The experimental results, the FPGA resource requirements for implementation of the processor in different configurations, and the comparisons with other similar processor architectures are presented in order to verify theoretical aspects proposed through this paper.

引用

页码：12441 / 12471

页数：31

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