FPGA implementation of hardware accelerated RTOS based on real-time event handling

Actual trends in the real-time system field consists of migration towards complex central processing unit (CPU) architectures with enhanced execution predictability and rapid CPU contexts switch, thus obtaining high-performant control systems. The main objective of this paper is to present the results obtained following the implementation of real-time operating systems (RTOS) functions in hardware. Based on the CPU resource multiplication concept, actual researches has been focused on synthesizing in field-programmable gate array (FPGA) and implementing innovative solutions to improve RTOS performance. The results are materialized by validating an efficient hardware scheduler micro-architecture, from which a remarkable efficiency and a plus of performance and predictability are obtained. The experimental results, the FPGA resource requirements for implementation of the processor in different configurations, and the comparisons with other similar processor architectures are presented in order to verify theoretical aspects proposed through this paper.