An expandable 36-channel neural recording ASIC with modular digital pixel design technique

被引：3

作者：

Wang, Quan ^{[1
,2
]}

Wang, Gang ^{[3
]}

You, Changhua ^{[4
]}

Zhang, Xuan ^{[5
]}

Liu, Daoyin ^{[6
]}

Zeng, Huanhuan ^{[6
]}

Xue, Ning ^{[4
]}

Yao, Lei ^{[6
]}

Li, Tie ^{[1
]}

机构：

[1] Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, Sci & Technol Microsyst Lab, Shanghai 200050, Peoples R China

[2] Univ Chinese Acad Sci, Beijing 100049, Peoples R China

[3] Shanghai Univ, Sch Microelect, Shanghai 200444, Peoples R China

[4] Chinese Acad Sci, Aerosp Informat Res Inst AIR, State Key Lab Transducer Technol, Beijing 100190, Peoples R China

[5] Shanghai Mtrix Technol Co Ltd, Shanghai 201800, Peoples R China

[6] Lingang Lab, Shanghai 200031, Peoples R China

来源：

ELECTRONICS LETTERS | 2023年 / 59卷 / 06期

基金：

国家重点研发计划;

关键词：

analogue integrated circuits; biomedical electronics; CMOS analogue integrated circuits; neural chips;

D O I：

10.1049/ell2.12765

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design and implementation of an expandable neural recording ASIC for multiple-channel neural recording applications. The ASIC consists of 36 modular digital pixels (MDPs) and a global digital controller (GDC) circuit. Each MDP has an analog frontend (AFE) circuit, a 12-bit successive approximation register ADC (SAR ADC), and a local digital controller (LDC) circuit. It achieves 5.9-mu V input referred noise (IRN), 10.8-effective number of bits (ENOB), 37.8-mu W power consumption, and 0.095 mm(2) area per channel. The ASIC is implemented in commercial SMIC 0.18-mu m CMOS process and validated by in-vivo experiment on a lab mouse with a 36-channel silicon-based neural probe.

引用

页数：3

共 29 条

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