Interface Trap Density of Commercial 1.7 kV SiC Power MOSFETs

The gate oxide interface traps strongly influence the device threshold voltage stability, channel mobility and reliability. This paper characterizes the interface trap density from commercial state-of-the-art 1.7 kV SiC MOSFETs. The subthreshold slope method was used to extract the interface trap density, and C-V curves were performed to add insight into the oxide charges. The devices presented an interface trap density of around 10(13) cm(-2) eV(-1) near the conduction band edge and interface states distributed along the bandgap. These results provide essential information on the gate oxide reliability status of such commercial devices under consideration for industrial and photovoltaic applications.