LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks

被引:1
|
作者
Lo, Yun-Chen [1 ]
Tsai, Yu-Chih [1 ]
Liu, Ren-Shuo [1 ]
机构
[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 300044, Taiwan
关键词
Index Terms-Approximate computation; floating point; latency-versatile architecture;
D O I
10.1109/LCA.2023.3287096
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Computing latency is an important system metric for Deep Neural Networks (DNNs) accelerators. To reduce latency, this work proposes LV, a latency-versatile floating-point engine (FP-PE), which contains the following key contributions: 1) an approximate bit-versatile multiplier-and-accumulate (BV-MAC) unit with early shifter and 2) an on-demand fixed-point-to-floating-point conversion (FXP2FP) unit. The extensive experimental results show that LV outperforms baseline FP-PE and redundancy-aware FP-PE by up to 2.12x and 1.3x speedup using TSMC 40-nm technology, achieving comparable accuracy on the ImageNet classification tasks.
引用
收藏
页码:125 / 128
页数:4
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