Investigation of SiGe/Si heterojunction inductive line tunneling TFET with source Schottky contact for prospect ultra-low power applications

In this paper, a SiGe/Si heterojunction inductive line tunneling tunnel field-effect transistor with source Schottky contact (SC HJLT-iTFET) is proposed and investigated by the Sentaurus Technology Computer Aided Design (TCAD) simulator. By utilizing an appropriate source Schottky metal, the need for multiple ion implantation and annealing steps required for traditional P-I-N TFETs can be avoided, and the problems of self-alignment and random dopant fluctuations (RDF) during ion implantation can be solved. A high ON-state current (I ON) is obtained as fully overlapping the source and gate by line tunneling mechanism dominated, the appropriate Si1-x Ge x mole fraction material in the source region and high-k gate dielectric employed can further improve I ON. The incorporation of the block layer effectively decreases the lateral electric field at the drain end to reduce the OFF-state current (I OFF). Furthermore, the proposed charge enhancement layer (CEL) on the SiGe channel can suppress the Fermi level pinning effect (FLP) and enhance the charge of the source region. Based on the feasibility of the practical fabrication process, and the rigorous simulations indicate that the device has an SSavg of 19.8 mV/dec and SSmin of 6.8 mV/dec at V D = 0.2 V, I ON of 2.27 x 10-6 A mu m-1, and an I ON/I OFF ratio of 1.02 x 1010, with extremely fast switching speed. These features make the device suitable for future ultra-low power applications on the internet of things, artificial intelligence, and related fields.