Fast Performance Evaluation Methodology for High-speed Memory Interfaces

An increase in the data rate of memory interfaces causes higher inter-symbol interference (ISI). To mitigate ISI, recent high-speed memory interfaces have started employing complex datapath, utilizing equalization techniques such as continuous-time linear equalizer and decision-feedback equalizer. This incurs huge overhead for design verification with conventional methods using transient simulation. This paper proposes a fast and accurate verification methodology to evaluate the voltage and timing margin of the interface, based on the impulse sensitivity function. To take nonlinear circuit behavior into account, the small- and large-signal responses were separately calculated to improve accuracy, using the data obtained from the periodic AC and periodic steady-state analyses. This approach achieves high accuracy, with shmoo similarity rates of over 95 %, while also significantly reducing verification time, up to 23x faster. Moreover, two different methods are proposed for evaluating the multi-stage Rx performance, providing a trade-off between accuracy and efficiency that can be tailored to the specific purpose, e.g., the verification or design process.