Design of high-efficiency complex multiplier for fault-tolerant computation

被引：0

作者：

Chen, Zhuo ^{[1
]}

Du, Yuxuan ^{[1
]}

Cheng, Boyang ^{[2
]}

Shan, Weiwei ^{[1
]}

机构：

[1] Southeast Univ, Sch Elect Sci & Engn, Nanjing 210000, Peoples R China

[2] Notre Dame Univ, Sch Elect Engn, South Bend, IN USA

来源：

INTEGRATION-THE VLSI JOURNAL | 2023年 / 90卷

基金：

中国国家自然科学基金;

关键词：

Approximate computing; Fault -tolerant computing; Booth multiplier; RADIX-8 BOOTH MULTIPLIERS; APPROXIMATE;

D O I：

10.1016/j.vlsi.2023.02.002

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, two improved structures and a truncation strategy with compensation for complex multiplication are proposed. Simulation in 28-nm CMOS for hardware performance is provided. Compared to the general complex multiplier, the two accurately improved structures realize 18.58% and 20.80% power consumption reduction, respectively. The truncation strategy with compensation reduces power consumption by 46.8% and controls Mean Relative Error Distance (MRED) at 0.54%. To verify the practicability of the proposed architec-ture, our designs are applied to the Fast Fourier Transform (FFT) processor to comprehensively evaluate the error characteristics and circuit performance.

引用

页码：190 / 195

页数：6

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