A Wide-Range ISFET Readout Circuit with Low-Power Linearity Enhancement

This work presents a chemical readout system designed in TSMC 180nm technology. The proposed design has an input range of 0-1.8V, linearity (R-2) of over 0.997, high sensitivity of 600 KHz/pH, a maximum frame rate of 1.4 mu s and a small chip area. The readout system includes an Ion-Sensitive Field Effect Transistor (ISFET) front-end that works in the saturation region, trans-linear circuits for linearity enhancement, and a CCO (Current Controlled Oscillator)-based ADC as an analogue to digital converter. This system was designed to provide a good balance between input range, linearity, and silicon area. The proposed architecture is capable of compensating for 400mV of trapped charge by changing the biasing current of the lineariser as a universal quadratic equation solver.