MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR

This work presents a RTL to C compiler called MIRROR that maximizes the re-usability of the generated C code for High-Level Synthesis (HLS). The uniqueness of the compiler is that it generates C code by using libraries of precharacterized RTL micro-structures that are uniquely identifiable through perceptual hashes. This allows to quickly generate C descriptions that include arrays and loops. These are important because HLS tools extensively use synthesis directives in the form of pragmas to control how to synthesize these constructs. E.g., arrays can be synthesized as registers or RAM, and loops fully unrolled, partially unrolled, not unrolled, or pipelined. Setting different pragma combinations lead to designs with unique area vs. performance and power trade-offs. Based on this, the main goal of our compiler is to parse synthesizable RTL descriptions specified in Verilog which have a fixed micro-architecture with specific area, performance and power profile and generate C code for HLS that can then be re-synthesized with different pragma combinations generating a variety of new micro-architectures with different area vs. performance trade-offs. We call this 'maximizing the re-usability of the RTL code because it enables a path to re-target any legacy RTL description to applications with different constraints. In particular we deal with pipelined descriptions in this work due to their uniqueness. Experimental results show that our proposed compiler is very effective, opening the door to automating the re-optimization of legacy hardware designs previously manually optimized using low level Hardware Description Languages (HDLs). We aim at making this compiler framework open source and available to the research community.