A Compact Energy-Saving D-Band Frequency Quadrupler with-1 dB Conversion Gain in 22 nm FDSOI

被引：0

作者：

Engelmann, Andre ^{[1
]}

Probst, Florian ^{[1
]}

Hetterle, Philip ^{[1
]}

Weigel, Robert ^{[1
]}

机构：

[1] Friedrich Alexander Univ Erlangen Nurnberg, Inst Elect Engn, Erlangen, Germany

来源：

2023 ASIA-PACIFIC MICROWAVE CONFERENCE, APMC | 2023年

关键词：

CMOS; D-band; FDSOI; frequency multiplier; MMIC; quadrupler; signal generation;

D O I：

10.1109/APMC57107.2023.10439882

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a compact and energy-saving D-band frequency multiplier by 4 (quadrupler) integrated into an advanced 22nm fully-depleted silicon-on-insulator (FDSOI) technology. The circuit consists of a multi-phase driven two-stage push-push doubler architecture achieving a conversion gain of -1 dB and covers a bandwidth of 23 GHz centered at 133 GHz. At 0.8V supply voltage, the quadrupler attains a maximum output power of dBm and an efficiency of 1.71% while consuming only 27mW of DC power. A harmonic rejection greater than 26 dBc is reached over the entire bandwidth. The core cell of the circuit occupies a compact chip area of 325 x 250 mu m(2).

引用

页码：303 / 305

页数：3

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