Intellectual Property Protection of Deep-Learning Systems via Hardware/Software Co-Design

被引:1
|
作者
Chen, Huili [1 ,5 ]
Fu, Cheng [2 ]
Rouhani, Bita Darvish [3 ]
Zhao, Jishen [2 ]
Koushanfar, Farinaz [4 ]
机构
[1] Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92093 USA
[2] Univ Calif San Diego, Comp Sci & Engn Dept, La Jolla, CA 92093 USA
[3] Microsoft, Redmond, WA 98052 USA
[4] Univ Calif San Diego, Elect & Comp Engn, La Jolla, CA 92093 USA
[5] Univ Calif San Diego, La Jolla, CA 92093 USA
关键词
Hardware; Fingerprint recognition; Security; Watermarking; IP networks; Computational modeling; Performance evaluation; Intellectual property protection; Deep learning hardware; Attestation; Digital fingerprinting;
D O I
10.1109/MDAT.2023.3303435
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Editor's notes: This article protects deep learning models by leveraging hardware device-specific model fingerprinting and trusted execution environment. - Gang Qu, University of Maryland, USA © 2013 IEEE.
引用
收藏
页码:23 / 31
页数:9
相关论文
共 50 条
  • [21] Hardware Software Co-design in Haskell
    Aronsson, Markus
    Sheeran, Mary
    ACM SIGPLAN NOTICES, 2017, 52 (10) : 162 - 173
  • [22] Hierarchical hardware/software co-design
    Niculiu, T
    Burileanu, D
    Manolescu, A
    Becker, J
    Glesner, M
    SIMULATION IN INDUSTRY'99: 11TH EUROPEAN SIMULATION SYMPOSIUM 1999, 1999, : 697 - 699
  • [23] Automatic software hardware co-design for reconfigurable computing systems
    Saha, Proshanta
    2007 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLS 1 AND 2, 2007, : 507 - 508
  • [24] Software-Hardware Co-design for Fast and Scalable Training of Deep Learning Recommendation Models
    Mudigere, Dheevatsa
    Hao, Yuchen
    Huang, Jianyu
    Jia, Zhihao
    Tulloch, Andrew
    Sridharan, Srinivas
    Liu, Xing
    Ozdal, Mustafa
    Nie, Jade
    Park, Jongsoo
    Luo, Liang
    Yang, Jie
    Gao, Leon
    Ivchenko, Dmytro
    Basant, Aarti
    Hu, Yuxi
    Yang, Jiyan
    Ardestani, Ehsan K.
    Wang, Xiaodong
    Komuravelli, Rakesh
    Chu, Ching-Hsiang
    Yilmaz, Serhat
    Li, Huayu
    Qian, Jiyuan
    Feng, Zhuobo
    Ma, Yinbin
    Yang, Junjie
    Wen, Ellie
    Li, Hong
    Yang, Lin
    Sun, Chonglin
    Zhao, Whitney
    Melts, Dimitry
    Dhulipala, Krishna
    Kishore, K. R.
    Graf, Tyler
    Eisenman, Assaf
    Matam, Kiran Kumar
    Gangidi, Adi
    Chen, Guoqiang Jerry
    Krishnan, Manoj
    Nayak, Avinash
    Nair, Krishnakumar
    Muthiah, Bharath
    Khorashadi, Mahmoud
    Bhattacharya, Pallab
    Lapukhov, Petr
    Naumov, Maxim
    Mathews, Ajit
    Qiao, Lin
    PROCEEDINGS OF THE 2022 THE 49TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA '22), 2022, : 993 - 1011
  • [25] 1st Workshop on Software and Hardware Co-Design of Deep Learning Systems in Accelerators (SHDA23)
    Shu, Tong
    Lim, Seung-Hwan
    Balaji, Pavan
    Bhowmick, Sanjukta
    ACM International Conference Proceeding Series, 2023, : 1757 - 1758
  • [26] LACC:a hardware and software co-design accelerator for deep neural networks
    于涌
    Zhi Tian
    Zhou Shengyuan
    HighTechnologyLetters, 2021, 27 (01) : 62 - 67
  • [27] LACC: a hardware and software co-design accelerator for deep neural networks
    Yu Y.
    Zhi T.
    Zhou S.
    High Technology Letters, 2021, 27 (01) : 62 - 67
  • [28] Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip
    Thepayasuwan, N
    Damle, V
    Doboli, A
    21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, : 126 - 133
  • [29] Hardware/software co-design for DSP applications via the HMS framework
    Sheliga, M
    Sha, EHM
    1996 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, CONFERENCE PROCEEDINGS, VOLS 1-6, 1996, : 1248 - 1251
  • [30] PipeFL: Hardware/Software co-Design of an FPGA Accelerator for Federated Learning
    Wang, Zixiao
    Che, Biyao
    Guo, Liang
    Du, Yang
    Chen, Ying
    Zhao, Jizhuang
    He, Wei
    IEEE ACCESS, 2022, 10 : 98649 - 98661