共 18 条
- [1] Materials to System Co-optimization (MSCO™) for SRAM and its application towards Gate-All-Around Technology International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2023, : 53 - 56
- [2] Design Technology Co-optimization for Enabling 5nm gate-all-around Nanowire 6T SRAM 2015 INTERNATIONAL CONFERENCE ON IC DESIGN & TECHNOLOGY (ICICDT), 2015,
- [3] Gate-All-Around SRAM: Performance Investigation and Optimization Towards Vccmin Scaling 2024 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW, 2024,
- [4] Gate-All-Around FET Based 6T SRAM Design Using a Device-Circuit Co-Optimization Framework 2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2017, : 1113 - 1116
- [5] Nanosheet Width Investigation for Gate-All-Around Devices Targeting SRAM Application 2021 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2021), 2021, : 19 - 22
- [8] Soft-Error Sensitivity in SRAM Manufactured by Bulk Gate-All-Around (GAA) Technology 2024 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS 2024, 2024,
- [9] Materials Technology Co-optimization of Self-Aligned Gate Contact for Advanced CMOS Technology Nodes 2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2020,
- [10] Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology 34TH IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (SOCC), 2021, : 25 - 28