Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems

被引:0
|
作者
Nakabeppu, Shota [1 ]
Yamasaki, Nobuyuki [1 ]
机构
[1] Keio Univ, Dept Informat & Comp Sci, Yokohama 2238522, Japan
关键词
non-volatile flip-flop; non-volatile memory; embedded real-time system; fault-tolerant system; microprocessor architecture; NONVOLATILE; MEMORY;
D O I
10.1587/transele.2022CDP0005
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
It is very important to design an embedded real-time system as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little performance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5 mu sec and almost hide the overhead of checkpoint creations. The non-stop microprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.
引用
收藏
页码:365 / 381
页数:17
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