A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application

This paper proposes a novel sense-amplifier-based flip-flop (SAFF) applied in low-power, high-speed operation. With the employment of the pre-charge control technique and shut-off transistor, the power and delay of the proposed SAFF are significantly reduced. Furthermore, the proposed SAFF can provide low-voltage operation. Post-layout simulation results based on the SMIC 55 nm CMOS process show that the proposed SAFF achieves a 28.9% reduction in the CLK-to-Q delay and a 53.2% decrease in power (25% input data switching activity) and the power-delay product of the proposed SAFF shows 3.0x improvement compared with the conventional SAFF.