Low-Power and Low-Latency Hardware Implementation of Approximate Hyperbolic and Exponential Functions for Embedded System Applications

The hyperbolic and exponential functions are widely used in various applications in engineering fields such as machine learning, Internet of Things (IOT), signal processing, etc. To fulfill the needs of future applications effectively, this paper proposes a low-latency, low-power, acceptable accuracy, and low-cost architecture for computing the approximate exponential function e(+/- z) and the hyperbolic functions sinh(z) and cosh(z) using a table-driven algorithm named Approximate Composited-Stair Function (ApproxCSF). By adopting a FPGA, the proposed design is realized and demonstrates significant improvements in terms of latency, hardware cost, power consumption, and MSE by 91%, 96%, 74%, and 99%, respectively, compared to the state-of-the-art. Xilinx Virtex-5/7 FPGAs have been employed throughout the functional verification and prototype processes. Compared to related works, it shows that the proposed architectures are much better for low-cost and low-latency computations of exponential and hyperbolic functions than CORDIC, stochastic computation, and the Look-up Table approaches. The source code is publicly available online https://github.com/AyadMDalloo/ApproxCSF.