Exploring the Influence of Material Properties of Epoxy Molding Compound on Wafer Warpage in Fan-Out Wafer-Level Packaging

被引:5
|
作者
Chuang, Wan-Chun [1 ]
Huang, Yi [1 ]
Chen, Po-En [1 ]
机构
[1] Natl Sun Yat sen Univ, Engn Technol Res & Promot Ctr, Dept Mech & Electromech Engn, Kaohsiung 804, Taiwan
关键词
fan-out wafer-level packaging; warpage; epoxy molding compound; finite element analysis; EXPERIMENTAL-VERIFICATION; SIMULATION; OPTIMIZATION;
D O I
10.3390/ma16093482
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
This study investigated the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. As there is currently a lack of comprehensive discussion on the various material property parameters of EMC materials, it is essential to identify the critical influencing factors and quantify the effects of each parameter on wafer warpage. The material properties include Young's modulus of the epoxy molding compound before and after the glass transition temperature (Tg) range of 25-35 degrees C (E-L) and 235-260 degrees C (E-H), coefficient of thermal expansion (a1, a2), and the temperature change ( increment T) between E-L and E-H. Results show that, within the range of extreme values of material properties, E-L and a1 are the critical factors that affect wafer warpage during the decarrier process in fan-out packaging. a1 has a more significant impact on wafer warpage compared with E-L. E-H, a2, Tg, and increment T have little influence on wafer warpage. Additionally, the study identified the optimized material property of the epoxy molding compound that can reduce the maximum wafer warpage in the X and Y directions from initial values of 7.34 mm and 7.189 mm to 0.545 mm and 0.45 mm, respectively, resulting in a reduction of wafer warpage of 92.58% (X direction) and 93.74% (Y direction). Thus, this study proposes an approach for evaluating the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. The approach aims to address the issue of excessive wafer warpage due to material variation and to provide criteria for selecting appropriate epoxy molding compounds to enhance process yield in packaging production lines.
引用
收藏
页数:15
相关论文
共 50 条
  • [41] Warpage Prediction and Optimization for Embedded Silicon Fan-Out Wafer-Level Packaging Based on an Extended Theoretical Model
    Chen, Cheng
    Yu, Daquan
    Wang, Teng
    Xiao, Zhiyi
    Wan, Lixi
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2019, 9 (05): : 845 - 853
  • [42] Simulation and Experimental Study of the Warpage of Fan-Out Wafer-Level Packaging: The Effect of the Manufacturing Process and Optimal Design
    Wu, Mei-Ling
    Lan, Jia-Shen
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2019, 9 (07): : 1396 - 1405
  • [43] On the optimization of molding warpage for wafer-level glass interposer packaging
    Bao, Shuchao
    Li, Wei
    He, Yimin
    Zhong, Yi
    Zhang, Long
    Yu, Daquan
    JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2023, 34 (12)
  • [44] On the optimization of molding warpage for wafer-level glass interposer packaging
    Shuchao Bao
    Wei Li
    Yimin He
    Yi Zhong
    Long Zhang
    Daquan Yu
    Journal of Materials Science: Materials in Electronics, 2023, 34
  • [45] REDISTRIBUTION-LAYERS FOR FAN-OUT WAFER-LEVEL PACKAGING AND HETEROGENEOUS INTEGRATIONS
    Lau, John H.
    2019 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2019,
  • [46] Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging
    Lau, John H.
    Li, Ming
    Li, Qingqian Margie
    Xu, Iris
    Chen, Tony
    Li, Zhang
    Tan, Kim Hwee
    Yong, Qing Xiang
    Cheng, Zhong
    Wee, Koh Sau
    Beica, Rozalia
    Ko, C. T.
    Lim, Sze Pei
    Fan, Nelson
    Kuah, Eric
    Kai, Wu
    Cheung, Yiu-Ming
    Ng, Eric
    Xi, Cao
    Ran, Jiang
    Yang, Henry
    Chen, Y. H.
    Lee, N. C.
    Tao, Mian
    Lo, Jeffery
    Lee, Ricky
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2018, 8 (06): : 991 - 1002
  • [47] Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging
    Lianto, Prayudi
    Tan, Chin Wei
    Peng, Qi Jie
    Jumat, Abdul Hakim
    Dai, Xundong
    Fung, Khai Mum Peter
    See, Guan Huei
    Chong, Ser Choong
    Ho, Soon Wee David
    Soh, Siew Boon Serine
    Lim, Seow Huang Sharon
    Chua, Hung Ming Calvin
    Haron, Ahmad Abdillah
    Lee, Huan Ching Kenneth
    Zhang, Mingsheng
    Ko, Zhi Hao
    San, Ye Ko
    Leong, Henry
    2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020), 2020, : 1126 - 1131
  • [48] Fan-out Wafer Level Packaging of GaN Traveling Wafer Amplifier
    Schwantuschke, D.
    Ture, E.
    Braun, T.
    Nguyen, T. D.
    Wohrmann, M.
    Pretl, M.
    Engels, S.
    2022 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS 2022), 2022, : 579 - 582
  • [49] Active Device Performance after Fan-out Wafer-level Packaging Process
    Li, Hong-Yu
    Kawano, Masaya
    Lim, Simon
    Cereno, Daniel Ismael
    Sekhar, Vasarla Nagendra
    2018 IEEE 20TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2018, : 495 - 499
  • [50] Realization of the potential of fan-out wafer level packaging
    Carson, Flynn
    Advancing Microelectronics, 2010, 37 (03): : 10 - 12