Device Design Direction of CSTBT for Low Loss and EMI Noise

被引：1

作者：

Nishi, Koichi ^{[1
]}

Konishi, Kazuya ^{[2
]}

Tadakuma, Toshiya ^{[1
]}

Furukawa, Akihiko ^{[1
]}

Saito, Wataru ^{[3
]}

机构：

[1] Mitsubishi Electr Corp, Power Device Works, Fukuoka 8190192, Japan

[2] Mitsubishi Electr Corp, Adv Technol Res & Dev Ctr, Kobe, Hyogo 6618661, Japan

[3] Kyushu Univ, Res Inst Appl Mech, Fukuoka 8168580, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2023年 / 70卷 / 12期

关键词：

Electromagnetic interference; Logic gates; Surges; Capacitance; Germanium; Switches; Electric potential; Carrier stored trench-gate bipolar transistor (CSTBT); electromagnetic interference (EMI) noise; insulated gate bipolar transistor (IGBT); negative gate capacitance; IGBT;

D O I：

10.1109/TED.2023.3326794

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article presents the electromagnetic interference (EMI) noise mechanism of carrier stored trench-gate bipolar transistor (CSTBT). We experimentally and numerically analyze structural parameter dependencies of the EMI noise of CSTBT. It has been clear that the gate voltage lift-up derives from a negative gate capacitance at the side of the carrier stored layer (CS-layer) and leads to a current surge increase, which results in EMI noise. The EMI noise can be reduced by a decrease in gate-collector capacitance and transconductance and an increase in gate-emitter capacitance and threshold voltage.

引用

页码：6144 / 6150

页数：7

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