Performance Evaluation of Mesh-based NoCs:Implementation of a New Architecture and Routing Algorithm

被引:1
|
作者
Sudhanshu Choudhary [1 ]
Shafi Qureshi [1 ]
机构
[1] Indian Institute of Technology
关键词
Interconnects; network on chip (NoC); routing; traffic; switching;
D O I
暂无
中图分类号
TN47 [大规模集成电路、超大规模集成电路];
学科分类号
080903 ; 1401 ;
摘要
This paper presents the result of experiments conducted in mesh networks on different routing algorithms, traffic generation schemes and switching schemes. A new network on chip (NoC) topology based on partial interconnection of mesh network is proposed and a routing algorithm supporting the proposed architecture is developed. The proposed architecture is similar to standard mesh networks, where four extra bidirectional channels are added which remove the congestion and hotspots compared to standard mesh networks with fewer channels. Significant improvement in delay (60% reduction) and throughput (60% increase) was observed using the proposed network and routing when compared with the ideal mesh networks. An increase in number of channels makes the switches expensive and could increase the area and power consumption. However, the proposed network can be useful in high speed applications with some compromise on area and power.
引用
收藏
页码:403 / 413
页数:11
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