Low leakage 3×VDD-tolerant ESD detection circuit without deep N-well in a standard 90-nm low-voltage CMOS process

被引：0

作者：

YANG ZhaoNian ^{[1
]}

LIU HongXia ^{[1
]}

WANG ShuLong ^{[1
]}

机构：

[1] Key Laboratory of Wide Bandgap Semiconductor Materials and Devices of Ministry of Educ13ation,School of Microelectronics,Xidian University

来源：

Science China(Technological Sciences) | 2013年 / 08期

基金：

中国国家自然科学基金;

关键词：

detection circuit; electrostatic discharge(ESD); leakage current; over-stress voltage; stacked-transistors;

D O I：

暂无

中图分类号：

TN386.1 [金属-氧化物-半导体（MOS）器件];

学科分类号：

0805 ; 080501 ; 080502 ; 080903 ;

摘要：

A new low leakage 3×VDD-tolerant electrostatic discharge(ESD)detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process.Stacked-transistors technique is adopted to sustain high-voltage stress and reduce leakage current.No NMOSFET operates in high voltage range and it is unnecessary to use any deep N-well.The proposed detection circuit can generate a 38 mA current to turn on the substrate triggered silicon-controlled rectifier(STSCR)under the ESD stress.Under normal operating conditions,all the devices are free from over-stress voltage threat.The leakage current is 88 nA under 3×VDD bias at 25°C.The simulation result shows the circuit can be successfully used for 3×VDD-tolerant I/O buffer.

引用

页码：2046 / 2051

页数：6