Packaging Challenges and Solutions For Next Generation Low-Profile WLCSP

Owing to its small footprint, fine pitch capability, low profile, known process flow, and low cost, Wafer Level Chip Scale Package (WLCSP) has been a very fundamental package option for a host of applications such as consumer mobile, portable and wearable products, Internet of Things (IoT) for Power Management, Bluetooth/WiFi, Audio, NFC. Etc. As the driving force of thinner electronic needs and its applications, hence, it is worth exploring the low-profile WLCSP from a package structure, manufacturability, reliability and performance standpoint. In this study, successfully developed a low-profile 4-Layer WLCSP package with the die thickness below 200um for maximum total package height of 250um and 200um. Based on the references of current mass production capability for 300um package stack-up, two test vehicles were designed for maximum package thicknesses of 250um and 200um with die thicknesses down to 105um and 90um respectively using 300mm wafer size. Both test vehicles follow standard 4-Layer WLCSP structure with two dielectric layers as passivation, one Redistribution Layer (RDL), and one Under Bump Metallization (UBM) layer. The main achievement of this work is mitigating the risks associated with low-profile WLCSP as they relate to reliability performance. Board Level Reliability Thermal Cycling Test (BLR-TCT) reliability simulations were carried out to assess the influence of various parameters including die thickness, bump height standoff as well as effects of different UBM sizes. Design of Experiment (DoE) and process engineering characterizations were also carried out to assess and mitigate key assembly challenges such as warpage handling, grinding and de-taping, laser marking recipe studies, dicing parameters, and ball placement evaluations. Both test vehicles successfully passed Package Level Reliability (PLR) and Board Level Reliability (BLR) performance dictated by future product requirements and target mission profiles.