Single Event Upset and Radiation Hardening of the Complementary FET (CFET) based 6T-SRAM

被引：0
|
作者：
Zhang, Zhengxin [1 ]
Chen, Wangyong [1 ]
Lin, Jianwen [1 ]
Cai, Linlin [1 ]
机构：
[1] Sun Yat Sen Univ, Sch Microelect Sci & Technol, Guangzhou 510275, Peoples R China
来源：
2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 | 2024年
关键词：
CFET; 6T-SRAM; SEU; LET threshold value; radiation hardening;
D O I：
10.1109/ISEDA62518.2024.10617634
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The CFET architecture addresses sub-3 nm technology challenges by reducing transistor footprint while maintaining performance. Our study employs 3D TCAD simulations to analyze SEU in four CFET 6T-SRAM architectures, identifying sensitive areas and LET thresholds. We propose a staggered architectures to enhance radiation Hardening and simplify routing, alongside structural optimizations for enhanced SEU hardening. These advancements aim to bolster reliability and efficiency in next generation semiconductor technologies.
引用
收藏
页码：782 / 782
页数：1
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