Design of logic circuits on 5 nm MOS

被引:0
|
作者
Chakraborty, Raktim [1 ]
Mandal, Jyotsna Kumar [1 ]
机构
[1] Univ Kalyani, Dept Comp Sci & Engn, Kalyani, India
关键词
logic gate circuits using CMOS; 5 nm gate length; CMOS; MOSFET; MOSFETS;
D O I
10.1088/1402-4896/ad963c
中图分类号
O4 [物理学];
学科分类号
0702 ;
摘要
In this research, MOSFET, CMOSFET of gate length 5 nm has been presented. The simulation at gate length of 5 nm has been conducted using three different semiconductor materials which are SiGe, InGaAs and GaN. The comparison among their performance at MOSFET level has been showcased which reveals the better performance of InGaAs among the three different semiconductor candidates which is functioning at threshold voltage of 0.3804 V, drive current of 4.431 x 10(-06) A mu m(-1) and low leakage current of 7.696 x 10(-11) A mu m(-1) respectively. The comparison with the existing MOSFETs have been carried out and validated with ITRS 2013 and IRDS 2020 respectively. In order to design 2 input AND, OR, XOR, XNOR, NAND, NOR and NOT gate circuits, the CMOSFET at 5 nm gate length has been utilised and their performance in terms of Average power, Propagation delay, Power delay product and noise margin analysis are furnished in this paper. A comparison among the proposed work with the existing reveals the lower power consumption, delay and the power delay product of the proposed work.<br />
引用
收藏
页数:7
相关论文
共 50 条
  • [1] A Methodology for the Design of MOS Current-Mode Logic Circuits
    Caruso, Giuseppe
    Macchiarella, Alessio
    IEICE TRANSACTIONS ON ELECTRONICS, 2010, E93C (02): : 172 - 181
  • [2] COMPLEMENTARY DYNAMIC MOS LOGIC CIRCUITS
    VITTOZ, E
    OGUEY, H
    ELECTRONICS LETTERS, 1973, 9 (04) : 77 - 78
  • [4] A Device Design for 5 nm Logic FinFET Technology
    Ding, Yu
    Luo, Xin
    Shang, Enming
    Hu, Shaojian
    Chen, Shoumian
    Zhao, Yuhang
    2020 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2020 (CSTIC 2020), 2020,
  • [5] Design and analysis of logic circuits based on 8 nm double gate MOSFET
    Kundu, Shrabanti
    Mandal, Jyotsna Kumar
    MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2024, 31 (5): : 1057 - 1074
  • [6] Design and simulation of logic circuits by combined single-electron/MOS transistor structures
    Li, Qin
    Cai, Li
    Zhou, Youjie
    Wu, Gang
    Wang, Sen
    2008 3RD IEEE INTERNATIONAL CONFERENCE ON NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS, VOLS 1-3, 2008, : 210 - +
  • [7] LOGIC DESIGN .5. CLOCK-DRIVEN CIRCUITS
    HOLDSWORTH, B
    ZISSOS, D
    WIRELESS WORLD, 1977, 83 (1498): : 52 - 55
  • [8] Design technique of neuron MOS binary circuits based on multiple-valued logic
    Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
    Pan Tao Ti Hsueh Pao, 2006, 7 (1316-1320):
  • [9] DESIGN AND IMPLEMENTATION OF 3-VALUED LOGIC SYSTEMS WITH MOS INTEGRATED-CIRCUITS
    MOUFTAH, HT
    SMITH, KC
    IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1980, 127 (04): : 165 - 168
  • [10] DESIGN MOS CIRCUITS ON A COMPUTER
    KUBINEC J
    Electronic Design, 1970, 18 (13): : 68 - 70